Tags :siemens-eda

Siemens Solido Simulation Suite 2025: AI-Accelerated Custom IC Verification The Solido Simulation Suite 2025 is Siemens EDA’s comprehensive, AI-powered solution for the simulation and verification of custom analog, mixed-signal, RF, and memory integrated circuits (ICs). It integrates advanced SPICE, FastSPICE, and mixed-signal simulators into a unified platform, leveraging AI to accelerate verification tasks for next-generation designs. Key New Features & Capabilities AI-Accelerated Verification Order-of-Magnitude Speedup: The AI-driven Solido Sim AI and Solido LibSPICE can deliver significant reductions in simulation time. In a collaboration with Samsung Foundry, this technology enabled a 14x speedup in standard cell library verification by reducing the required simulation samples by 80% while maintaining high accuracy. Automated Workflows: One-click automation replaces manual processes, transforming tasks like parameter...

Siemens Xpedition Enterprise 2510 for Linux | Advanced PCB Design & Systems Integration Platform Siemens Xpedition Enterprise 2510 for Linux is a high-performance, end-to-end electronic systems design platform. This Linux-native release provides a unified environment for complex printed circuit board (PCB) design, including system architecture, multi-board planning, advanced IC packaging, and signal/power integrity analysis. Core Functionality Overview: Unified Systems-to-Silicon Design Flow: Integrates system architecture definition, schematic capture, advanced PCB layout (HDI, rigid-flex), and IC packaging design within a collaborative, constraint-driven environment. Advanced Analysis & Verification: Includes integrated tools for high-speed signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMC) analysis to ensure performance and reliability of complex designs. Team Collaboration & Data Management: Built on a centralized, scalable data...

Tanner Tools 2024.3 for Linux | Comprehensive IC & MEMS Design Suite Tanner Tools 2024.3 for Linux is a complete, Linux-native integrated circuit (IC) and MEMS design suite, providing an end-to-end flow from schematic entry and simulation to physical layout and verification for analog/mixed-signal, power management, and MEMS devices. Core Functionality Overview: Full-Custom Analog/Mixed-Signal Design: Integrated environment for schematic capture (S-Edit), SPICE and FastSPICE simulation (T-Spice), and physical layout (L-Edit) with design rule checking (DRC) and layout vs. schematic (LVS) verification. MEMS & Multi-Domain Simulation: Specialized tools for designing and simulating micro-electro-mechanical systems (MEMS), enabling co-simulation of mechanical, thermal, and electrostatic effects within the IC design flow. Advanced Verification & Interoperability: Includes parasitic extraction, post-layout simulation, and support for industry-standard...

Mentor OneSpin 2025 for Linux | Advanced Formal Verification & Assertion-Based Design Platform Mentor OneSpin 2025 for Linux is a high-performance, Linux-native formal verification software suite for ensuring the functional correctness and security of semiconductor designs and electronic systems. It provides exhaustive mathematical proof capabilities for RTL and gate-level verification beyond traditional simulation. Core Functionality Overview: Exhaustive Formal Property Verification (FPV): Enables the formal proof of complex design properties, assertions, and compliance checks (e.g., AMBA, PCIe protocols) to achieve 100% coverage for critical logic paths. Advanced Equivalence Checking & Security Verification: Performs exhaustive RTL-to-RTL and RTL-to-netlist equivalence checking, alongside specialized tools for detecting hardware security vulnerabilities (Trojans, side-channels). Assertion Synthesis & IP Integrity Verification: Automatically generates assertions from simulation traces...

Mentor Tessent 2025 | Comprehensive Semiconductor Test & Silicon Lifecycle Management Platform Mentor Tessent 2025 is a market-leading, end-to-end software platform for semiconductor test, yield analysis, and in-system monitoring. It provides a unified solution for design-for-test (DFT), manufacturing test, and silicon lifecycle management (SLM) from pre-silicon design to post-silicon deployment. Core Functionality Overview: Unified DFT & Test Automation: Integrated environment for implementing and verifying advanced test structures, including scan, memory BIST, logic BIST (LBIST), and analog test, streamlining the path from RTL to test patterns. Silicon Lifecycle Management & Analytics: Tools for embedding on-chip monitors (PPM, sensors) and developing in-system test/health management firmware, enabling data-driven yield learning and reliability monitoring. High-Quality Test Generation & Diagnostics: Advanced ATPG for high fault...

Questa OneSpin Static Formal 2025: The Exhaustive Verification Platform for Zero-Defect Designs Questa OneSpin Static Formal 2025 represents the industry’s most advanced static formal verification platform, designed for engineers who require mathematical certainty in their ASIC, FPGA, and IP designs. Unlike traditional simulation, which tests only a subset of possible scenarios, static formal verification uses rigorous mathematical proof techniques to exhaustively analyze a design against its specifications. This makes it an indispensable tool for verifying safety-critical hardware in automotive (ISO 26262), aerospace, and medical applications where a single undetected bug can have catastrophic consequences. Core Technology & Key Capabilities: 1. Formal Property Verification (FPV) This is the flagship application, enabling engineers to prove that a design’s behavior matches its intended...